1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a full complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell.
2. Description of the Related Art
Among semiconductor memory devices, static random access memories (SRAMs) consume less power than and operate faster than dynamic random access memories (DRAMs). Thus, SRAMs are widely used for cache memory devices for computers or portable electronic products.
Memory cells for SRAMs are largely divided into two types; one is a high load resistor cell having a high resistance as its load element, and the other is a CMOS cell having a PMOS transistor as its load element. CMOS cells are subdivided into two types; one is a thin film transistor cell having a thin film transistor as its load element, and the other is a fall CMOS cell having a bulk transistor as its load element.
FIG. 1 is a schematic equivalent circuit diagram of a general CMOS cell. Referring to FIG. 1, the CMOS cell includes a pair of driver transistors TD1 and TD2, a pair of transfer transistors TA1 and TA2, and a pair of load transistors TL1 and TL2. In the circuit shown in FIG. 1, the pair of driver transistors TD1 and TD2 and the pair of transfer transistors TA1 and TA2 are all NMOS transistors, while the pair of load transistors TL1 and TL2 are both PMOS transistors.
The first driver transistor TD1 and the first transfer transistor TA1 are serially connected to each other. A source region of the first driver transistor TD1 is connected to a ground line Vss, and a drain region of the first transfer transistor TA1 is connected to a first bit line BL. Likewise, the second driver transistor TD2 and the second transfer transistor TA2 are serially connected to each other. A source region of the second driver transistor TD2 is connected to the ground line Vss, and a drain region of the second transfer transistor TA2 is connected to a second bit line/BL. The second bit line/BL retains the inverted information of the first bit line BL.
Source and drain regions of the first load transistor TL1 are connected to a power line Vcc and a drain region of the first driver transistor TD1 at a first node, respectively. Likewise, source and drain regions of the second load transistors TL2 are connected to the power line Vcc and a drain region of the second driver transistor TD2 at a second node, respectively. A gate electrode of the first driver transistor TD1 and a gate electrode of the first load transistor TL1 are both connected to the second node. A gate electrode of the second driver transistor TD2 and a gate electrode of the second load transistor TL2 are both connected to the first node. Also, gate electrodes of the first and second transfer transistors TA1 and TA2 are connected to a word line WL.
The above-described CMOS cell has a small standby current and a large noise margin compared to the load resistor cell. Thus, CMOS cells are widely used for high-performance SRAMs which require a low power voltage.
Equivalent circuits of the CMOS SRAM cell shown in FIG. 1 can be implemented on semiconductor substrates in various configurations. In particular, in SRAMs, the parasitic capacitance of a bit line is closely related to the operating speed of an SRAM device. Therefore, the parasitic capacitance of a bit line must be designed to be as small as possible, and the resistance of a bit line must be low. As a result, it is often desirable that bit lines and the spaces between them be wide, i.e., that the bit lines high large pitch.
It is an object of the present invention to provide a full CMOS SRAM cell which can maximize the pitch of bit lines.
The present invention provides a full complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell including first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line. The first common source region is the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line. The second common source region is the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.
In one embodiment, the first and second active regions can be formed in a first conductivity type well and a second conductivity type well, respectively. The first and second conductivity types can be N-type and P-type, respectively.
In one embodiment, the first active region can be formed in a xe2x80x9cTxe2x80x9d shape. The second active region can be formed in an upside-down or inverted xe2x80x9cTxe2x80x9d shape symmetrical with the first active region. The second active region can include extending portions which extend from ends of both wings of the inverted xe2x80x9cTxe2x80x9d shape in a direction opposite to the first active region. The word line can traverse the extending portions of the second active region.
The word line, the first gate electrode and the second gate electrode can be formed by patterning a first conductive layer. The ground line and the power line can be formed of a second conductive layer different from the first conductive layer. Here, the word line may be formed of a conductive layer different from the first and second gate electrodes. Also, the first and second bit lines can be formed of a third conductive layer different from the first and second conductive layers.
The full CMOS SRAM cell can further include a first local interconnection for electrically connecting a portion of the second active region, a portion of the first active region and the second gate electrode, wherein the part of the second active region faces the second common source region among the second active regions at both sides of the, first gate electrode, and the part of the first active region faces the first common source region among the first active regions at both sides of the first gate electrode. The full CMOS SRAM cell can also include a second local interconnection for electrically connecting a portion of the second active region, a portion of the first active region and the first agate electrode, wherein the part of the second active region faces the second common source region among the second active regions at both sides of the second gate electrode and the part of the first active region faces the first common source region among the first active region at both sides of the second gate electrode. Here, the first and second active regions electrically connected to the second gate electrode correspond to a first node region, and the first-and second active regions electrically connected to the first gate electrode correspond to a second node region. In one embodiment, the first and second local interconnections can be formed of a second conductive layer. Also, in one embodiment, the first and second bit lines can be formed of a third conductive layer.
The word line and the second active region traversing the word line constitute first and second transfer transistors. The first gate electrode and the second active region traversing the first gate electrode constitute a first driver transistor, and the second gate electrode and the second active region traversing the second gate electrode constitute a second driver transistor. Likewise, the first gate electrode and the first active region traversing the first gate electrode constitute a first load transistor, and the second gate electrode and the first active region traversing the second gate electrode constitute a second load transistor. Consequently, the first and second load transistors are serially connected to each other in the first active region, and the first transfer transistor, the first driver transistor, the second driver transistor and the second transfer transistor are sequentially serially connected in the second active region.
The first and second driver transistors, and the first and second load transistors constitute a latch circuit, together with the first and second local interconnections. Thus, the first node region corresponds to the drain regions of the first driver transistor and the first load transistor and serves as a source region of the first transfer transistor. Also, the second node region corresponds to the drain regions of the second driver transistor and the second load transistor and serves as a source region of the second transfer transistor.
The first bit line is electrically connected to the drain region of, the first transfer transistor, that is, the first bit line contact region, and the second bit line is electrically connected to the drain region of the second transfer transistor, that is, the second bit lie contact region.
The first gate electrode serves as a common gate electrode shared by the first transfer transistor and the first load transistor. Likewise, the second gate electrode serves as a common gate electrode shared by the second transfer transistor and the second load transistor.
According to the present invention, only the first and second bit lines exist within a cell 30 pitch as interconnections formed of the third conductive layer. Therefore, the pitch of bit lines can be maximized. As a result, the parasitic capacitance of a bit line can be minimized, thereby improving the operating speed of the SRAM.